5.4 Application of Parameter Transmission Statement 144
5.5 Structural Description with Library Component 145
5.6 Compiling Directive Statement 147
5.6.1 Macro Definition Statement 147
5.6.2 File Inclusive Statement, 'include 148
5.6.3 Conditional Compilation Statement, 'ifdef, 'else, 'endif 149
5.7 Application of Attribute of Keep 150
5.8 Usage of SingalProbe 152
Exercises 154
Labs and Designs 157
Lab 5-1 High-speed Hardware Divider Design 157
Lab 5-2 Design of Various Types of Shift Registers 158
Lab 5-3 Verilog Code-based Frequency Meter Design 158
Lab 5-4 8-bit Adder Design 159
Lab 5-5 VGA Displayer Control Circuit Design 160
Chapter 6 The Usage of LPM Macro Module 165
6.1 The Example of Invoking Macro Module of Counter 165
6.1.1 The Invoking of the Text Code of the Counter LPM Module 165
6.1.2 Application of LPM Counter Code and Parameter Transmission Statement . 167
6.1.3 Project Creation and Simulation Testing 169
6.2 Example of Building Attribute Control Multiplier 169
6.3 Usage of Macro Block of LPM_RAM 171
6.3.1 Initialization File and Its Generation 172
6.3.2 Invoking LPM_RAM by Schematic Diagram Method 174
6.3.3 Test LPM_RAM 176
6.3.4 Expression of Memory Initialization File Loading of Verilog Code Description . 177
6.3.5 Structure Control of Memory Design 178
6.4 Usage Examples of LPM_ROM 180
6.4.1 Design of Simple Sinusoidal Signal Generator . 180
6.4.2 Hardware Implementation and Testing of Sinusoidal Signal Generator . 182
6.5 Application of In-System Memory Content Editor 183
6.6 Invoke of Embedded PLL of LPM 185
6.6.1 Building Embedded PLL Component 185
6.6.2 PLL Test . 188
6.7 The Usage of In-System Sources and Probes Editor 188
6.8 Principle and Application of DDS 191
6.8.1 Principle of DDS 192
6.8.2 Example of DDS Signal Generator 194
Exercises 195
Labs and Designs 196
Lab 6-1 Look-up Table based Hardware Operator Design 196
Lab 6-2 Sinusoidal Signal Generator Design 197
Lab 6-3 Design of Simple Data Acquisition System 197
Lab 6-4 DDS-based Sinusoidal Signal Generator Design 198
Lab 6-5 Phase-shifted Signal Generator Design 199
Lab 6-6 Amplitude-Modulated Signal Generator Design 200
Lab 6-7 Hardware-Based De-jitter Circuit Design 200
Chapter 7 Deep Understanding of Verilog HDL 203
7.1 Two Types of Assignment Statements in Process 203
7.1.1 Blocking Assignment with Unspecified Time-delay 203
7.1.2 Blocking Assignment with Specified Time-delay 204
7.1.3 Non-blocking Assignment with Unspecified Time-delay 205
7.1.4 Non-blocking Assignment with Specified Time-delay 207
7.1.5 Deep Understanding of the Features of Blocking and Non-blocking
Assignments 209
7.1.6 Further Discussion of Different Initialization Ways 211
7.2 Discussion of Procedural Statement 213
7.2.1 Conclusion of Procedural Statement Application 213
7.2.2 Relationship between Incomplete Conditional Statement and Sequential
Circuit 214
7.3 Design of Three-state and Bidirectional Port 217
7.3.1 Design of Three-state Control Circuit 217
7.3.2 Design of Bidirectional Port . 217
7.3.3 Design of Three-state Bus Control Circuit 220
7.4 Resource Optimization 222
7.4.1 Resource Sharing 223
7.4.2 Logic Optimization 224
7.4.3 Serialization 225
7.5 Speed Optimization 226
Exercises 229
Labs and Designs 230
Lab 7-1 Design of the Signal Detection Circuit of 4×4 Array Keyboard 230
Lab 7-2 Design of Direct Current Motor-based Synthesized Measurement and
Control System 232
Lab 7-3 Design of Control Module of VGA-based Simple Image Displaying 234
Lab 7-4 Design of Hardware-based Music Performing Circuit 235
Lab 7-5 Design of Electronic Organ Circuit based on PS2 Keyboard Control
Model 240
Chapter 8 Design Technology of State Machine 243
8.1 General Form of Verilog State Machine 243
8.1.1 Characteristics and Advantages of State Machine 243
8.1.2 General Structure of State Machine 245
8.1.3 Initial Control and Expression 249
8.2 Moore-type State Machine 250
8.2.1 State Machine with Multiprocess Structure 251
8.2.2 Sequence Detector and Its State Machine Design 255
8.3 Mealy-type State Machine 257
8.4 State Machine with Different Coding Types 260
8.4.1 Direct Output Coding 260
8.4.2 Defining the State Coding with the Use of Macro Definition Statement 262

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